1. Field of the Invention
This invention relates to the field of operational amplifier output stages, and particularly to high output current, low distortion, rail-to-rail output stages.
2. Description of the Related Art
The characteristics of an operational amplifier (op amp) are defined with various specifications. Three of these, i.e., maximum output current, quiescent current, and distortion, tend to be interrelated. For example, the quiescent current, i.e., the current drawn from the power supplies when no signal is applied to the op amp, tends to limit the maximum output current, with an increase in maximum output current requiring a corresponding increase in quiescent current. An increase in quiescent current also tends to improve the distortion performance of the op amp, though at the cost of higher power dissipation.
A known op amp output stage is shown in FIG. 1, which is a simplified schematic of the output stage of an AD8041 op amp from Analog Devices, Inc. in Norwood, Mass. A drive circuit 10 produces complementary drive signals 12 and 14 to drive a complementary pair of output transistors Q1 and Q2, respectively. Q1 and Q2 are connected in series between supply voltages VCC and VEE, with the junction of their collectors serving as the stage's output terminal OUT. Q1 and Q2 conduct respective currents I.sub.Q1 and I.sub.Q2 in response to drive signals 12 and 14, which are summed at the output terminal to produce an output current I.sub.o.
Drive circuit 10 is arranged to receive differential inputs V+ and V-, and to produce complementary drive signals 12 and 14 in response; i.e., as drive signal 12 pulls down harder on Q1's base to increase the current I.sub.Q1 conducted by Q1 to the output, drive signal 14 also decreases to reduce the current I.sub.Q2 conducted by Q2. Similarly, drive circuit 10 manipulates drive signals 12 and 14 so that when I.sub.Q2 is increased, I.sub.Q1 is decreased.
A number of implementations can be employed to obtain the A/B-type behavior from drive circuit 10, one of which is illustrated in FIG. 1. Differential inputs V- and V+ are connected to transistors Q3 and Q4, respectively, each of which is connected as an emitter follower. V- and V+ are also connected to transistors Q5 and Q6, which are also connected as emitter followers; Q3 and Q4 are of opposite polarity to that of Q5 and Q6. A pair of transistors Q7 and Q8 are connected to receive the outputs of emitter follows Q3 and Q4, respectively, and to conduct first and second currents in response. A pair of transistors Q9 and Q10 are connected to receive the outputs of emitter follows Q5 and Q6, respectively, and to conduct third and fourth currents in response. A current mirror circuit 16 made from transistors Q11 and Q12 is connected to mirror the current conducted by Q7 to Q8, with the difference current between the mirrored current and the Q8 current being drive signal 14. Similarly, a current mirror 18 made from transistors Q13 and Q14 is connected to mirror the current conducted by Q9 to Q10, with the difference current between the mirrored current and the Q10 current being drive signal 12. The emitters of Q7 and Q9 are connected together at a junction 20 and the emitters of Q8 and Q10 are connected together at a junction 22. A compensation capacitor is connected between V- and OUT, and a resistor RI is connected between junctions 20 and 22 to improve the stage's stability. A complementary pair of clamp transistors Q15 and Q16 are biased with respective bias voltages V.sub.bias1 and V.sub.bias2 to prevent current mirror transistors Q14 and Q12, respectively, from saturating.
The output stage also includes a transistor Q17 connected between mirror transistor Q11 and VCC via a resistor R2, and a transistor Q18 connected between mirror transistor Q13 and VEE via a resistor R3. Q17/R2 and Q18/R3 are part of the scheme to bias output transistors Q1 and Q2 at the proper quiescent current. The collector currents of Q17 and Q18 are mirrored via Q11/Q12 and Q13/Q14, respectively, to provide known currents through Q15 and Q16. This, along with bias voltages V.sub.bias1 and V.sub.bias2, and the relative sizes of Q1, Q15, Q2 and Q16 set the output transistors' quiescent operating point.
In operation, when V- drops below V+, the voltages at the bases of Q7 and Q9 decrease. This results in the current through Q7 and Q10 (via R1) to be increased, and that through Q8 and Q9 to decrease. The Q10 current is greater than the mirrored Q9 current, and the resulting difference current (drive signal 12) pulls down on the base of output transistor Q1, increasing the current IQ. provided to the output terminal. At the same time, the mirrored Q7 current is greater than the Q8 current, and the resulting difference current (drive signal 14) reduces the drive to Q2, and thereby reduced I.sub.Q2. With IQ.sub.1 increased and I.sub.Q2 decreased, the net output current I.sub.out is increased.
Similarly, when V+ falls below V-, more current flows through the Q9/R1/Q8 path, and less flows through the Q10/R1/Q7 path, increasing the drive to output transistor Q2 and reducing it to Q1, producing a net reduction in I.sub.o.
The maximum amount of current from Q1 is limited by the amount of current conducted by Q10, which is in turn limited by the current sources I4 and I1 connected in series with follower transistors Q3 and Q6. Specifically, the maximum current from Q1 is given by the lesser of 1).beta..sub.Q1 *.beta..sub.Q10 *I4 and 2).beta..sub.Q1 *.beta..sub.Q7 *I1. Similarly, Q2 is limited by the amount of current conducted by Q8, which is limited by the current sources I2 and I3 connected in series with follower transistors Q4 and Q5, with the maximum current from Q2 given by the lesser of 1).beta..sub.Q2 *.beta..sub.Q9 *I3 and 2).beta..sub.Q2 *.beta..sub.Q8 *I2. Thus, the stage's quiescent current depends on the magnitudes of the I1-I4 currents, along with the relative sizes of several of the transistor' emitters. Increasing I1-I4 increases the maximum value of I.sub.o, though doing so also increases the stage's quiescent current and power dissipation.
The stage's quiescent current also affects its distortion performance. Some nonlinearity is introduced into the output by the driver stage, primarily due to the behavior of transistors Q7-Q10 as they act to sink and source the required base currents needed by the output transistors. The magnitude of the nonlinearity is directly related to the percentage change of the currents through Q7-Q10. Increasing the stage's quiescent current lowers this percentage change, which reduces the nonlinearity and thus improves the distortion performance. However, as noted above, increasing quiescent current causes a corresponding and often undesirable increase in power dissipation.